1. Field of the Invention
The present invention relates to a display device and, more particularly to a liquid crystal display device and a method of driving a liquid crystal display device.
2. Discussion of the Related Art
In general, a liquid crystal display device displays images by individually supplying data signals to liquid crystal cells arranged in a matrix configuration and controlling light transmittance of the liquid crystal cells. Accordingly, the liquid crystal display device includes a liquid crystal display panel with the liquid crystal cells by the unit of a pixel arranged in the matrix configuration and a driving circuit for driving the liquid crystal cells.
The liquid crystal display panel includes a color filter substrate and a thin film transistor array substrate attached together with a certain gap therebetween, and a liquid crystal material layer formed in the gap between the color filter substrate and the thin film transistor array substrate. On the thin film transistor array substrate of the liquid crystal display panel, a plurality of data lines transmitting image information to the liquid crystal cells and a plurality of gate lines transmitting a scan signal to the liquid crystal cells intersect, and liquid crystal cells are defined at every intersection of the data lines and gate lines. A common electrode and a pixel electrode are formed at each of facing inner surfaces of the color filter substrate and the thin film transistor array substrate to supply an electric field to the liquid crystal layer. The pixel electrode is formed at every liquid crystal cell of the thin film transistor array substrate, while the common electrode is integrally formed along an entire surface of the color filter substrate. Accordingly, by controlling voltages supplied to the pixel electrode when the common electrode receives a voltage, light transmittance of liquid crystal cells may be individually controlled.
In order to control the voltage supplied to the pixel electrode by liquid crystal cells, each liquid crystal cell includes a thin film transistor applied as a switching device. The driving circuit includes a gate driving unit supplying a scan signal to the gate lines, a data driving unit supplying image information to the data lines, a timing controller controlling a driving timing of the gate driving unit and the data driving unit, and a power supply unit supplying various driving voltages used for a liquid crystal display device.
The timing controller controls a driving timing of the gate driving unit and the data driving unit through image information and a control signal supplied from an external graphic processor. The timing controller also supplies image information to the data driving unit.
The power supply unit generates driving voltages, such as a common voltage (Vcom), a gate high voltage (Vgh), a gate low voltage (Vgl) or a gamma reference voltage (Vref) used for the liquid crystal display device by using power supplied from the external graphic processor. The power supply unit supplies the driving voltages to the gate driving unit, the data driving unit, a gamma voltage generator, and the liquid crystal display panel.
The gate driving unit sequentially supplies scan signals to the gate lines so that the liquid crystal cells arranged in the matrix configuration can be selected line-by-line, and image information is supplied to the liquid crystal cells of the selected one line from the data driving unit by way of the data lines.
When the image information is individually supplied to the pixel electrode of the liquid crystal cells and the common voltage (Vcom) is supplied to the common electrode, a voltage difference occurs between the pixel electrode and the common electrode, according to which an electric field is supplied to the liquid crystal material layer. Thus, light transmittance of the liquid crystal cells are individually controlled to display a desired image.
The data driving unit and the gate driving unit, which are directly connected to the liquid crystal display panel, are integrated with a plurality of integrated circuits (IC). The data driving ICs and the gate driving ICs are respectively mounted on a tape carrier package (TCP) and connected to the liquid crystal display panel in a tape automated bonding (TAB) method, or the data driving ICs and the gate driving ICs are respectively mounted on the liquid crystal display panel in a chip on glass (COG) method.
The data driving ICs and gate driving ICs mounted on the TCP and connected to the liquid crystal display panel in the TAB method receive control signals and DC voltages input from outside through signal lines mounted on a printed circuit board (PCB) connected to the TCP and are connected to each other. That is, the data driving ICs are connected in series to each other through the signal lines mounted on the data PCB and receive image information, control signals and drive voltages applied from the timing controller and the power supply unit.
The gate driving ICs are connected in series to each other through signal lines mounted on the gate PCB and receive control signals and driving voltages supplied from the timing controller and the power supply unit.
FIG. 1 is a schematic plan view of a liquid crystal display device according to the related art. In FIG. 1, a liquid crystal display device includes a liquid crystal display panel 1, a plurality of data TCPs 8 connected between one longer side of the liquid crystal display panel 1 and a data PCB 12, a plurality of gate TCPs 14 connected between one shorter side of the liquid crystal display panel 1 and a gate PCB 13, data driving ICs 10 respectively mounted at the data TCPs 8, and gate driving ICs 16 respectively mounted at the gate TCPs 14.
The liquid crystal display panel 1 is formed as a thin film transistor (TFT) array substrate 2 and a color filter (CF) substrate 4 attached together and facing each other with a certain gap therebetween, and a liquid crystal material layer (not shown) is formed in the gap.
The one shorter side and one longer side of the TFT array substrate 2 protrudes compared with the CF substrate 4, and a gate pad part and a data pad part are provided at the protruded region of the TFT array substrate 2. At the region where the TFT array substrate 2 and the CF substrate 4 are attached together, an image display part 21 is formed on which pixels are arranged in a matrix configuration. At the image display part 21 of the TFT array substrate 2, a plurality of gate lines 20 are arranged horizontally and connected to the gate pad part, and a plurality of data lines 18 are arranged vertically and connected to the data pad part. Accordingly, the gate lines 20 and the data lines 18 intersect, and pixels having a TFT and a pixel electrode are individually provided at the intersection and arranged in a matrix form.
At the image display part 21 of the CF substrate 4, there are provided red, green, and blue color filters coated by a black matrix, and a common electrode forming an electric field at the liquid crystal material layer together with the pixel electrode provided at the TFT array substrate 2.
An input pad 24 and an output pad 25 electrically connected to the data driving ICs 10 are formed at the data TCPs 8. The input pad 24 of the data TCPs 8 is electrically connected to the data PCB 12, and the output pad 25 of the data TCPs 8 is electrically connected to the data pad part of the thin film transistor array substrate 2. The data driving ICs 10 convert digital signals into analog signals and supply them to the data lines 18 of the liquid crystal display panel 1.
An input pad 28 and an output pad 29 electrically connected to the gate driving ICs 16 are formed at the gate TCPs 14. The input pad 28 of the gate TCPs 14 is electrically connected to the gate PCB 13, while the output pad 29 of the gate TCPs 14 is electrically connected to the gate pad part of the thin film transistor array substrate 2.
The gate driving ICs 16 sequentially supply the scan signal to the gate lines 20 of the liquid crystal display panel 1. The data PCB 12 and the gate PCB 13 respectively include connectors 55 and 65 to receive control signals and driving voltages through a flexible plate cable (FPC) 70 from outside.
In general, the liquid crystal display device shows changed picture quality characteristics depending on a main viewing angle at which a viewer views a screen. For example, for a liquid crystal display device applied to a notebook computer, its main viewing angle is determined by a direction that a viewer views a screen from an upper side as much as a predetermined angle on the basis of a direction vertical to the screen. When a liquid crystal display panel is installed with a certain height at a public place or a public traffic means (i.e., bus, train, or airplane), its main viewing angle is determined by a direction that a viewer views a screen from a lower side as much as a certain angle on the basis of a direction vertical to a screen.
Meanwhile, when a liquid crystal display device is applied to an audio/visual system or various information displays installed between a driver's seat and a passenger's seat, its main viewing angle is determined by a direction that a viewer views a screen from a left side or a right side as much as a certain angle on the basis of a direction vertical to the screen. Accordingly, the liquid crystal display device is fabricated such that an image is horizontally and vertically reversed according to a usage environment.
In order to reverse an image of the liquid crystal display device vertically or horizontally, the liquid crystal display device includes a first controller 51 provided at the gate PCB 13, which applyies a first control signal (UP/DOWN) to the gate driving ICs 16 through the gate TCPs 14 to vertically reverse an image displayed on the image display part 21 of the liquid crystal display panel 1, and a second controller 52 provided at the data PCB 12, which applyies a second control signal (LEFT/RIGHT1) to the data driving ICs 10 through the data TCPs 8 to horizontally reverse an image displayed on the image display part 21 of the liquid crystal display panel 1.
FIGS. 2A to 2C are schematic diagrams showing normal, reversed, and inverted images as displayed on an image display part of a liquid crystal display panel according to the related art. First, with reference to FIG. 2A, when the first control signal (UP/DOWN1) with a high potential is supplied to the gate driving ICs 16 through the gate TCPs 14 and the second control signal (LEFT/RIGHT1) with a low potential is supplied to the data driving ICs 10 through the data TCPs 8, gate lines 18 provided at the image display part 21 are sequentially driven from the first one to the last one. Image information is thus applied by the unit of the gate line from the left side to the right side from the data driving ICs 10 through the data TCPs 8, whereby an image is normally displayed on the image display part 21.
With reference to FIG. 2B, when the first control signal (UP/DOWN1) with a high potential is supplied to the gate driving ICs 16 through the gate TCPs 14 and the second control signal (LEFT/RIGHT1) with a high potential is applied to the data driving ICs 10 through the data TCPs 8, the gate lines 18 provided at the image display part 21 are sequentially driven from the first one to the last one. Image information is thus supplied from the right side to the left side from the data driving ICs 10 through the data TCPs 8, whereby an image is reversed and displayed on the image display part 21. 10025With reference to FIG. 2C, when the first control signal (UP/DOWN1) with a low potential is supplied to the gate driving ICs 16 through the gate TCPs 14 and the second control signal (LEFT/RIGHT1) with a low potential is supplied to the data driving ICs 10 through the data TCPs 8, the gate lines 18 provided at the image display part 21 are sequentially driven from the last one to the first one. Thus, image information is supplied from the left side to the right side from the data driving ICs 10 through the data TCPs 8, whereby an image is inverted and displayed on the image display part 21.
However, because the connectors 55 and 65 are respectively formed at the data PCB 12 and the gate PCB 13 and control signals and driving voltages are received through the FPC 70 from outside, the liquid crystal display device has the following problems. First, as the connectors 55 and 65 are respectively formed on the thin data PCB 12 and the thin gate PCB 13, the thickness of the liquid crystal display device is inevitably increased as high as the connectors 55 and 65, which makes it difficult to obtain a thin liquid crystal display device.
Second, because the FPC 70 needs to be installed to electrically connect the connectors 55 and 65, the number of processes for fabrication of a liquid crystal display device increases a unit cost of the liquid crystal display device also increases.
In order to avoid such problems, there has been proposed a technique to mount lines supplying control signals and drive voltages to the data PCB 12 and the gate PCB 13 are mounted at an outer dummy region of the thin film transistor array substrate 2 so that either the data PCB 12 or the gate PCB 13 can be removed. Accordingly, since the gate driving IC 16 needs fewer signals than the data driving IC 10, the gate PCB 13 is commonly removed.
In other words, the gate driving ICs 16 connected to the liquid crystal display panel 1 by the TAB method receive control signals and DC voltages from the data PCB 12 through line-on-glass (LOG) lines mounted on the thin film transistor array substrate 2 of the liquid crystal display panel 1, and are connected to each other.
FIG. 3 is a schematic plan view of a liquid crystal display device without a gate PCB according to the related art. In FIG. 3, a liquid crystal display device includes a liquid crystal display panel 101, a plurality of data TCPs 108 connected between one longer side of the liquid crystal display panel 101 and a data PCB 112, a plurality of gate TCPs 114 connected to one shorter side of the liquid crystal display panel 101, data driving ICs 110 mounted at each of the data TCPs 108, and gate driving ICs 116 mounted at each of the gate TCPs 114.
The liquid crystal display panel 101 is formed as a TFT array substrate 102 and a CF substrate 104 are attached together and face each other with a certain gap therebetween, and a liquid crystal material layer (not shown) is formed in the gap. The one shorter side and one longer side of the TFT array substrate 102 protrudes as compared with the CF substrate 104, and a gate pad part and a data pad part are provided at the protruded region of the TFT array substrate 102.
At the region where the TFT array substrate 102 and the CF substrate 104 are attached together, an image display part 121 is formed on which pixels are arranged in a matrix form. At the image display part 121 of the TFT array substrate 102, a plurality of gate lines 120 are arranged horizontally and connected to the gate pad part, and a plurality of data lines 118 are arranged vertically and connected to the data pad part. Accordingly, the gate lines 120 and the data lines 118 intersect, and pixels having a TFT and a pixel electrode are individually provided at the intersection and arranged in a matrix form.
At the image display part 121 of the CF substrate 104, there are provided red, green, and blue color filters coated by a black matrix, and a common electrode forming an electric field at the liquid crystal layer together with a pixel electrode provided at the TFT array substrate 102. The gate pad part and the data pad part provided at the protruded region of the TFT array substrate 102 are formed to correspond to the image display part 121. Thus, the corner portion where one shorter side and one longer side of the TFT array substrate 102 meet is a dummy region that is not used. But recently, LOG lines 126 are formed at the corner portion to supply control signals and driving voltages to the gate driving ICs 116.
Input pads 124 and output pads 125 electrically connected to the data driving IC 110 are formed at the data TCP 108. The input pads 124 of the data TCP 108 are electrically connected to the data PCB 112, and the output pads 125 of the data TCP 108 are electrically connected to the data pad part of the TFT array substrate 102.
A first data TCP 108 includes a gate signal transmission line 122 electrically connected to the LOG lines 126 mounted at the TFT array substrate 102. The gate signal transmission line 122 transmits gate control signals and gate driving voltages supplied from a timing controller and a power supply unit via the data PCB 112 to the LOG lines 126.
The data driving ICs 110 convert digital signals into analog signals and supply them to the data lines 118 of the liquid crystal display panel 101. At the gate TCP 114, gate driving ICs 116 are mounted, and in addition, gate signal transmission lines 128 electrically connected to the gate driving ICs 116 and output pads 130 are formed.
The gate signal transmission lines 128 are electrically connected to the LOG lines 126 mounted on the TFT array substrate 102, and the output pads 130 are electrically connected to the gate pad part of the TFT array substrate 102. The gate driving ICs 116 sequentially supply a scan signal, such as a gate high voltage signal (Vgh) and a gate low voltage signal (Vgl), to the gate lines 120 in response to gate control signals and gate driving voltages applied through the LOG lines 126 and the gate signal transmission lines 128.
Each LOG line 126 supplies DC voltage signals, such as the gate high voltage signal (Vgh), the gate low voltage signal (Vgl), a common voltage signal (Vcom), a ground signal (GND), and a power supply voltage signal (Vdd), supplied from a power supply unit and gate control signals, such as a gate start pulse (GSP), a gate shift clock (GSC), and a gate enable signal (GOE), supplied from the timing controller. The LOG lines 126 are patterned at the same time as when the gate lines and the gate electrodes are formed on the thin film transistor array substrate 102.
However, the related art of the liquid crystal display device without the PCB has the following problem. By applying the gate start pulse (GSP) to the gate driving IC through the line-on-glass line, the gate lines of the image display part may be sequentially driven from the first one to the last one, but conversely, it is not possible to drive the gate lines of the image display part from the last one to the first one. Therefore, because the vertical reversing of an image is not possible, it is limited to a usage environment.